Atrenta pioneered the RTL analysis with its SpyGlass tool and rapidly evolved SpyGlass into 2nd and 3rd generation tools. With Atrenta solution, design development is transformed into a continuous realization of design closure jumpstarted at RTL phase. With Atrenta impact, RTL handoff achieves multi-dimensional goals the traditional functional correctness as well as RTL readiness for synthesizability, testability, timing etc. Atrenta'SpyGlass and 1Team solutions take the uncertainty and chance out of electronic product creation, enabling customers to build better products, more quickly and economically than ever before.
Designation SE/SSE/LE-Synthesis/Optimization
Job Description Position Responsibilities
Development/ Maintenance of the Logic Optimizations within our Synthesis engine.
Develop/Innovate new algorithms/techniques for fast Multilevel Optimizations.
Improvement of existing RTL/Logic Optimization algorithms to improve QoR.
Development of FSM/Sequential optimizations within the current framework.
Lead a team of highly motivated engineers towards our next level Timing/Area QoR objectives (For Lead Engineers).
Desired Profile Skill Required
MUST Actual 1+ year experience using C/C++, Advanced data-structure & API based application development, Strong digital design concepts; familiarity with Verilog , VHDL.
Preferable 2-5 years experience working in EDA, specifically Synthesis environment. Knowledge of Synthesis Optimizations.
Knowledge of BDDs, SAT Solvers, Boolean Matching, Multilevel/Two-Level Optimizations will be a plus.
Knowledge of State Equivalence, Assignment algorithms will be a plus.
Hardware: Linux/ SUN Solaris
Software: UNIX, C, C++, Perl, CVS, Valgrind, Purify
Strong technical skills, aptitude and a good knowledge of data structures.
Fast Learner with an ability to multitask.
Email [email protected]